Metal gate electrodes are currently being investigated to replace polysilicon gate electrodes in today's ever shrinking and changing transistor devices. One of the principal reasons the industry is investigating replacing polysilicon gate electrodes with metal gate electrodes is to solve polysilicon depletion effects for future CMOS devices. Traditionally, polysilicon gate electrodes with overlying silicides have been used for the gate electrodes in CMOS devices. However, as device feature sizes continue to shrink, polysilicon depletion is becoming a serious issue.
Accordingly, metal gates have been proposed. However, in order to optimize the threshold voltage (Vt) in CMOS devices, metals with the appropriate work functions (e.g., from the silicon valence band to that of the conduction band) are required. For instance, the metal gates need tunable work functions for NMOS and PMOS devices similar to present polysilicon gate technology, requiring the work functions of metal gates to range from 4.1˜4.4 eV for NMOS and 4.8˜5.2 eV for PMOS (see, B. Cheng, B. Maiti, S. Samayedam, J. Grant, B. Taylor, P. Tobin, J. Mogab, IEEE Intl. SOI Conf. Proc., pp. 91–92, 2001).
Recently, silicided metal gates have been investigated based on the extension of existing self-aligned silicide (SALICIDE) technology. In this approach, polysilicon is deposited over the gate dielectric. A metal is deposited over the polysilicon and reacted to completely consume the polysilicon resulting in a fully silicided metal gate, rather than a deposited metal gate. The silicided metal gate provides a metal gate with the least perturbation to the conventional process and avoids contamination issues. Furthermore, poly doping has been shown to affect the work function of the silicided metal gates.
The silicided metal gates are not without their problems. One of the more significant problems associated with the silicided metal gates is attributed to the simultaneous formation of the silicided metal gate and the silicided source/drain regions. When formed simultaneously, the depth of the silicided source/drain regions is directly proportional to the thickness of the polysilicon gate electrode. As the polysilicon gate electrodes currently range in thickness from about 60 nm to about 120 nm, the silicided source/drain regions ultimately extend into the silicon substrate by up to about 60 nm to about 120 nm, respectively. Deep silicided source/drain regions are nonetheless undesirable.
Various companies in the industry have attempted to separate the silicidation of the polysilicon gate and the silicidation of the source/drain regions. Those companies employ chemical mechanical polishing (CMP) technology to decouple the polysilicon gate from the source/drain regions. In such integration schemes, the gate electrode is masked by a silicon oxide layer and a silicide is then formed on the source/drain regions. Next, a blanket dielectric layer is deposited over the gate stack and silicided source/drain regions. The CMP process is then employed to expose the gate electrode for silicidation, while the source/drain regions are covered by the protective dielectric layer. The main drawback of this approach originates from the across-wafer non-uniformity inherently associated with polishing (such as dishing, etc.). In addition, the poly height on the active area may be different from the designed poly height. As a result, the height of the poly gate after polishing may suffer significant variation. Therefore, the silicidation may be inconsistent across-wafer, and/or wafer-to-wafer due to the thickness variation in poly-gate.
Accordingly, what is needed is a method for manufacturing silicided metal gate structures separate from the silicided source/drain regions that does not experience the drawbacks of the prior art methods.